![]() These two LEON implementations were developed by ESA. The second LEON2 VHDL design was used in the processor device AT697 from Atmel (F) and various system-on-chip devices. ![]() The LEON family includes the first LEON1 VHSIC Hardware Description Language (VHDL) design that was used in the LEONExpress test chip developed in 0.25 μm technology to prove the fault-tolerance concept. ![]() The goals have been to detect and tolerate one error in any register without software intervention, and to suppress effects from Single Event Transient (SET) errors in combinational logic. To maintain correct operation in the presence of SEUs, extensive error detection and error handling functions were needed. Another objective was to be able to manufacture in a Single event upset (SEU) tolerant sensitive semiconductor process. The objectives for the project were to provide an open, portable and non-proprietary processor design, capable to meet future requirements for performance, software compatibility and low system cost. The LEON project was started by the European Space Agency (ESA) in late 1997 to study and develop a high-performance processor to be used in European space projects. 2 LEON processor models and distributions.
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